WLP

WLP, or wafer-level packaging, is a method of packaging integrated circuits at the wafer level, meaning that the packaging steps are completed while the dice are still part of the wafer rather than after individual die singulation. This approach can yield very small form factors and short interconnects, enabling high-density I/O and potential cost benefits at high production volumes.

The two main categories of WLP are Wafer-Level Chip-Scale Packaging (WLCSP) and Fan-Out Wafer-Level Packaging (FO-WLP). WLCSP produces a package that is essentially the same size as the die, with redistribution layers formed on the wafer and solder bumps or copper pillars for interconnection. FO-WLP extends the interconnect area beyond the die by redistributing I/O over a larger molded area, allowing more pins without increasing the die size.

Process steps commonly involved in WLP include thinning the wafer, applying and patterning a redistribution layer (RDL) to route signals to bump pads, depositing and forming bumps or copper pillars for electrical connections, and often encapsulating the die before singulation. Testing can occur at the wafer level before or after packaging, depending on the process.

Advantages of WLP include a very small package footprint, potential reductions in parasitic interconnects, shorter signal paths, and the alignment of packaging with high-volume manufacturing. Limitations and challenges involve moisture sensitivity considerations, solder bump reliability, mechanical stress and warpage, and in some cases limited power handling or thermal dissipation compared with traditional substrates.

WLP is widely used in mobile devices, sensors, imaging chips, and other high-volume applications where compact size and dense I/O are advantageous. Related concepts include chip-scale packaging, CSP, and different forms of FO-WLP.