FOWLP

Fan-out wafer-level packaging (FOWLP) is a wafer-level packaging technology that encapsulates a silicon die in a molded compound and fans out electrical connections beyond the die edge. By building redistribution layers on the molded surface, FOWLP creates I/O pads at the periphery of the package, enabling a higher I/O density in a compact form factor without a traditional substrate or leadframe.

The manufacturing flow typically begins with placing one or more dies on a temporary carrier. The dies are encapsulated with a mold compound to form a fan-out structure around each die. The molded wafer is thinned and planarized, after which copper redistribution layers are deposited and patterned to route signals to outer I/O pads. Solder balls, bumps, or copper pillars are formed on the outer redistribution to provide external interconnects. The wafer is then singulated into individual packages.

FOWLP offers a number of advantages, including a very low package profile, short interconnects that can improve electrical performance, and high I/O density with the ability to combine multiple functions in a single package. It allows fine-pitch routing and can be compatible with standard board assembly processes, reducing the need for large organic substrates.

Challenges for FOWLP include higher manufacturing costs and the need for careful process control to manage mold compound behavior, warpage, and reliability over time. Scale-up, material choices, and process integration are important for ensuring yield and long-term performance, particularly for high-temperature and high-stress applications.

Applications of FOWLP span mobile devices, cameras, RF modules, wireless and baseband subsystems, memory and logic packages, sensors, and other consumer electronics that benefit from a slim, high-density package.