SMMU

System Memory Management Unit (SMMU) is a hardware component that provides address translation and memory protection for devices that perform direct memory access (DMA). In ARM-based systems, the SMMU is a form of an I/O memory management unit (IOMMU), responsible for translating device-visible addresses to physical memory addresses and enforcing access permissions.

An SMMU sits between I/O devices and system memory and uses translation tables to map addresses. It applies memory attributes and permission checks for each access and reports faults when a device attempts an unauthorized or invalid operation. To improve performance, translation lookaside buffers (TLBs) cache translations. Modern SMMUs can support multiple translation modes and domains, enabling isolation between devices and processes.

In ARM architectures, the SMMU commonly implements Stage 1 and Stage 2 translations. Stage 1 translates the device-visible address to an intermediate address, while Stage 2 maps that address according to the guest or process context in virtualization scenarios. Some configurations may bypass certain stages when virtualization is not used. Features such as per-device or per-process address spaces (PID or PASID) facilitate device-assisted virtualization and sharing of memory across virtual machines or processes.

Use cases include enabling DMA for PCIe endpoints, graphics processing units, and network interfaces while maintaining protection boundaries between devices and software. The SMMU helps prevent a misbehaving device from corrupting memory or interfering with other devices, and it supports fault reporting to software handlers for rapid diagnosis.

Relation to CPUs and other IOMMUs: the SMMU is distinct from the CPU’s MMU, operating specifically on I/O translations. It is ARM’s implementation of the IOMMU concept; other vendors provide similar functionality, such as Intel VT-d and AMD-Vi. Versions such as SMMUv2 and SMMUv3 introduce enhancements like expanded address space, PASID support, and advanced fault handling.