PCIe

PCI Express (PCIe) is a high-speed serial computer expansion bus standard designed to replace older PCI and PCI-X architectures. It provides a point-to-point connection between a motherboard’s root complex and peripheral devices called endpoints, such as graphics cards, SSDs, network adapters, and capture devices. PCIe supports a scalable bandwidth model by aggregating multiple serial lanes into a single link (e.g., x1, x2, x4, x8, x16, or x32).

The architecture is layered, consisting of a physical layer that transmits electrical signals, a data link layer that handles link establishment and error detection, and a transaction layer that carries configuration and I/O requests. A PCIe link negotiates its speed and width during initialization, and can operate at a lower tier if necessary. Links are typically hot-pluggable and support dynamic reconfiguration and power management.

Generations and performance have advanced through PCIe from Gen 1 through Gen 5, with per-lane transfer rates approximately 2.5, 5, 8, 16, and 32 gigatransfers per second, respectively. Net data throughput per lane is lower due to encoding and protocol overhead; practical bandwidth scales with the number of lanes. PCIe 6.0 has been specified to deliver higher per-lane rates (and includes new signaling methods) to continue the trend of increasing bandwidth, with x16 configurations commonly used for high-performance devices.

Adoption and usage are widespread in modern systems, with PCIe serving as the primary interface for GPUs, NVMe solid-state drives, network cards, and many other expansion cards. PCIe maintains backward compatibility, allowing newer devices to operate in older slots at reduced speeds.