Loadstore

Load-store is a category of computer architecture in which all arithmetic and logical operations operate only on data in the processor's registers. Memory operands are not allowed for core instructions; data must be loaded from memory into a register, used in a register-to-register operation, and stored back to memory as needed. The memory access is thus limited to explicit load and store instructions, and the instruction set emphasizes register-register operations.

Characteristics: A common feature is a relatively large register file and a simple, regular instruction encoding. Because computation never happens directly on memory operands, the hardware can be optimized for rapid register access, pipelining, and parallel execution. This simplification is a hallmark of RISC-style designs and supports aggressive instruction-level parallelism.

Origins and usage: The load-store model is central to many modern RISC architectures. Prominent examples include MIPS, ARM, SPARC, RISC-V, and POWER. While some ISAs allow limited memory operands, the normative usage in these designs is to keep computational instructions register-based and to move data with explicit loads and stores.

Advantages and limitations: The approach simplifies processor design and improves instruction-level parallelism and compiler back-ends, contributing to higher clock rates and predictable performance. Trade-offs include increased code size and potentially more memory traffic for algorithms that operate intensively on large data structures, as each step may require additional loads and stores.

Relation to other architectures: In contrast, memory-to-memory architectures or some complex instruction set architectures may perform operations directly on memory operands, though modern ISAs often approximate load-store behavior for performance reasons.