pipelining

Pipelining is a technique in computer architecture that overlaps the execution of consecutive instructions by dividing processing into sequential stages. Each stage performs part of the work and passes intermediate results to the next stage via pipeline registers. In a typical design, several instructions are in different stages at once, increasing overall throughput without increasing the clock frequency.

A common five-stage pipeline consists of instruction fetch, decode, execute, memory access, and write-back. While one instruction is decoded, another may be fetched, and a third may be executed, enabling a continuous stream of work. Real gains depend on how well stages are balanced and how often hazards occur.

Hazards can reduce or nullify throughput. Structural hazards arise from resource conflicts, data hazards from dependent instructions, and control hazards from branches. Mitigation techniques include forwarding (data bypassing), hazard detection and stalls, as well as branch prediction and speculative execution to hide or reduce penalties.

Pipelining also appears in data processing and digital signal processing, where it is used to improve throughput on streaming workloads. Design involves trading depth against complexity, latency, and power. Deeper pipelines can boost steady throughput but increase penalties from mispredictions, cache misses, or stalls.