RISCV

RISC-V, often written RISC-V, is an open standard instruction-set architecture (ISA) for computer processors. It defines the set of base instructions and a modular design that allows implementations to include optional extensions while preserving ISA compatibility. The standard is designed to be simple, clean, and extensible, enabling both small microcontrollers and high-performance processors.

RISC-V originated from the University of California, Berkeley, as a research project in the 2010s. It was released as an open specification with permissive licensing to encourage participation and avoid vendor lock-in. Governance moved to RISC-V International (formerly the RISC-V Foundation), a member-driven standards organization that coordinates development and promotes adoption.

The base ISA comes in 32- and 64-bit forms, RV32I and RV64I, with an optional 128-bit RV128I for future use. Common extensions include M for multiply/divide, A for atomic operations, F for single-precision floating-point, D for double-precision floating-point, and C for compressed instructions. The ISA separates a user mode from privileged execution modes (Machine, Supervisor, User) and specifies a memory and exception handling model, enabling operating systems to run on RISC-V hardware.

RISC-V has an expanding ecosystem of open-source cores, toolchains, simulators, and boards. Notable cores include Rocket and BOOM from UC Berkeley and PicoRV32. Toolchains such as GCC and LLVM/Clang, along with binutils and simulators, support building software for multiple ISA widths. The open nature and licensing have spurred use in embedded systems, IoT, data centers, and research.

RISC-V aims to reduce cost and risk of processor development by providing a royalty-free, modifiable ISA with broad industry collaboration. It is widely used in education and research and increasingly deployed in commercial products. The standard continues to evolve through extensions for vector processing, privileged architecture, and other domains.