MIPS

MIPS is a family of reduced instruction set computer (RISC) architectures developed for general-purpose computing. Originating in the 1980s at Stanford University and commercialized by MIPS Computer Systems (later MIPS Technologies), the name stands for Microprocessor without Interlocked Pipeline Stages, a nod to its pipeline design philosophy that aims to simplify hardware interlocks by relying on compiler scheduling.

MIPS uses fixed 32-bit instructions and a small set of simple, regular formats. There are three instruction formats: R-type (op, rs, rt, rd, shamt) for register operations; I-type (op, rs, rt, immediate) for immediate values and memory access; and J-type (op, target) for jumps. The architecture provides 32 general-purpose registers, with $zero always reading as 0. Common register aliases include $t0–$t9 for temporaries, $s0–$s7 for saved values, $v0–$v1 for values returned from functions, and $a0–$a3 for function arguments. Special-purpose registers include $ra (return address), $sp (stack pointer), $gp (global pointer), and the HI/LO pair used for certain multiply/divide results. The instruction set covers arithmetic, logic, shifts, comparisons, as well as loads (lw) and stores (sw), branches (beq, bne), and jumps (j, jal).

MIPS emphasizes a load/store memory model and, in many implementations, a pipelined five-stage execution: instruction fetch, decode, execute, memory access, and write-back. Hazard management is typically handled by data forwarding and hazard detection units. Over its history, MIPS has evolved through several generations (I through V and beyond) and 32- and 64-bit variants. It has seen wide use in embedded systems, network devices, and education, with notable historical deployments in devices such as the Sony PlayStation (R3000) and various Silicon Graphics workstations, and ongoing presence in Linux and other ecosystems.