RISC

RISC stands for Reduced Instruction Set Computer, a CPU design philosophy that emphasizes a small, highly optimized set of instructions. RISC architectures aim to execute instructions at high speed by keeping instruction decoding simple and uniform, often enabling one instruction per clock cycle. A hallmark is the load/store model, where memory access is limited to dedicated load and store instructions, and all arithmetic or logic operations operate on registers. RISC typically favors a large number of registers, fixed-length instructions, simple addressing modes, and extensive use of pipelining to improve throughput. The result is a hardware design that is easier to implement efficiently and that relies on compilers to optimize instruction sequences.

The term and concept emerged in the 1980s as researchers explored how to increase performance by reducing the complexity of instruction decoding. Pioneering work in the United States led to projects like RISC I and RISC II at the University of California, Berkeley, and related efforts such as IBM's 801 and the Stanford MIPS project. The MIPS, SPARC, and ARM families became prominent pragmatic realizations of the RISC idea, each influencing processor development in different domains. In the 1990s and beyond, ARM—originating from Acorn and developed for efficiency—became dominant in mobile and embedded devices, while MIPS and SPARC evolved in various markets. More recently, the RISC-V initiative has provided an open, extensible RISC architecture aimed at broad adoption in academia and industry.

Today, most modern CPUs incorporate RISC-like principles in their instruction set design or underlying microarchitecture, even if implemented as complex, superscalar, out-of-order engines. The RISC concept remains influential as a framework for balancing hardware simplicity with compiler support and performance.