superscalar

A superscalar processor is a type of microprocessor architecture that can issue and execute more than one instruction per clock cycle. In contrast to scalar processors, which issue a single instruction each cycle, a superscalar design uses multiple instruction fetch and decode paths, along with several execution units, to exploit instruction-level parallelism in typical workloads.

Key ideas include duplicating functional units (such as multiple ALUs and floating-point units), as well as dispatch logic that can select and launch several independent instructions simultaneously. Achieving efficiency also relies on techniques such as out-of-order execution, register renaming, and dynamic scheduling, so that independent instructions can run in parallel even when earlier ones are still in flight. Branch prediction and speculative execution help keep all execution units busy by reducing stalls caused by control flow changes.

History and practice: The concept emerged in the 1980s and has since become a standard feature of mainstream CPUs. Early consumer processors such as Intel's Pentium introduced dual-issue pipelines, while later generations expanded the degree of parallelism and added sophisticated out-of-order engines. Modern processors commonly combine superscalar execution with out-of-order, speculative techniques, large caches, and memory subsystem optimizations.

Limitations: The actual speedups depend on available instruction-level parallelism and memory behavior. Dependencies between instructions, cache misses, and mispredicted branches reduce effective utilization of multiple issue slots. Also, increasing the number of pipelines yields diminishing returns due to complexity and power costs.

See also: instruction-level parallelism, out-of-order execution, register renaming, branch prediction.