MCLK

MCLK, short for master clock, is a clock signal used to synchronize the operation of digital components within a system. It serves as a reference timing source that can drive other clocks and data transfers, ensuring coordinated operation across devices such as processors, audio codecs, and memory controllers. In many designs, MCLK is generated by an oscillator or PLL and distributed to multiple components that require a common timing reference.

In audio applications, MCLK is commonly the clock input to digital-to-analog converters (DACs), analog-to-digital converters (ADC), and digital audio interfaces such as I2S. The MCLK frequency is typically a multiple of the audio sampling rate, often 256x or 512x the target rate. For example, 11.2896 MHz corresponds to 44.1 kHz when using a 256x multiple, and 12.288 MHz corresponds to 48 kHz with a similar multiplier. The MCLK is then used to derive other essential clocks, such as the bit clock (BCLK) and word select (LRCLK), either inside the codec or by the host controller through additional PLLs or clock dividers. A device can act as the MCLK master, providing the clock to slaves, or as a slave, accepting a clock from a master.

Beyond audio, MCLK can refer to the memory clock in computing hardware, the clock that drives memory modules or the memory bus in GPUs and CPUs. The exact meaning of MCLK can vary by vendor, and some contexts use memory clock as distinct from the system clock. Implementations must consider clock integrity, jitter, and proper routing to maintain data reliability, especially in high-speed or multi-channel configurations.