PLLs

Phase-locked loop (PLL) is a control system that generates an output signal whose phase is locked to a reference signal. A PLL typically consists of a phase detector, a loop filter, a voltage-controlled oscillator (VCO), and a feedback path that feeds the VCO output back to the phase detector. The goal is to synchronize the output phase and frequency with the reference while allowing a controlled offset or division to achieve desired frequencies.

In operation, the phase detector compares the phase (and sometimes frequency) of the reference signal with the feedback signal derived from the VCO. The resulting error signal, after filtering, adjusts the VCO control input. The loop drives the phase difference toward zero, achieving phase and frequency alignment. When locked, the output frequency tracks the reference, often scaled by a divider in the feedback path. The loop has a capture (pull-in) range and a hold (lock) range that determine how far the input frequency can deviate while the loop can acquire and maintain lock.

There are analog and digital implementations. Analog PLLs use continuous-time phase detectors and loop filters, such as RC circuits or active filters, to shape the error signal. Digital PLLs use digital phase-frequency detectors and numerically controlled oscillators, implemented in DSPs or FPGAs, and may include all-digital or fractional-N architectures for fine frequency synthesis.

PLLs are widely used in communications and electronics for frequency synthesis, clock generation, clock recovery in data communications, demodulation, and jitter reduction. Key design considerations include loop bandwidth, phase noise, jitter, lock time, and stability.