CoWoS

CoWoS, short for Chip-on-Wafer-on-Substrate, is a packaging technology developed by Taiwan Semiconductor Manufacturing Company (TSMC). It is a 2.5D/3D integrated circuit packaging method that places one or more dies on a silicon interposer, which sits on a conventional organic substrate. The interposer contains through-silicon vias and redistribution layers that route signals between the logic die(s) and high-bandwidth memory or other chips, enabling high-density, high-bandwidth connections with lower latency than traditional packages.

CoWoS uses silicon interposers with TSVs; components are assembled using microbumps or solder bumps. In 2.5D configurations, a logic die (or multiple) are placed on the interposer, while memory stacks such as HBM are placed on the other side of the interposer and connected through the TSV network. The technology improves memory bandwidth, reduces interconnect length, and enables heterogeneous integration of dissimilar process nodes.

Introduced by TSMC in the 2010s, CoWoS has been used in high-performance computing, data-center accelerators, and AI chips that require large bandwidth between memory and logic. It has been deployed with memory technologies such as High Bandwidth Memory (HBM) and HBM2, often in GPUs and AI accelerators, to achieve high aggregate bandwidth.

Limitations include higher manufacturing complexity and cost, limited substrate sizes, and a relatively long design cycle. The interposer-based approach also constrains scaling compared with monolithic 2.5D/3D approaches and has faced competition from alternative packaging such as fan-out wafer-level packaging (FO-WLP).

Today, CoWoS remains a prominent solution for select high-performance products where memory bandwidth is critical, though broader mass-market adoption is limited by cost and yield considerations.