HBM

High Bandwidth Memory (HBM) is a type of dynamic random-access memory designed to deliver very high memory bandwidth with lower power consumption by stacking multiple DRAM dies and connecting them with through-silicon vias to a processor via a silicon interposer. By using 3D stacking and wide, short interconnects, HBM reduces pin count and routing length, enabling close physical proximity to a graphics processor or other accelerator.

HBM stacks typically consist of several DRAM dies bonded face-to-face. A common arrangement uses four dies per stack, each contributing to a wide aggregate data interface; together they present a high-bandwidth connection to the memory controller, often around a 1024-bit-wide interface per stack. The stacks sit on or beside the logic die on a silicon interposer, connected by microbumps. The interposer provides dense routing between memory and processor with short electrical paths, improving bandwidth and latency.

HBM1 appeared in the mid-2010s, notably with AMD’s Fiji-based GPUs and early HBM implementations. HBM2 and later HBM2E expanded capacity and data rates, allowing multiple stacks and larger total memory. HBM3 has been pursued by several vendors to push bandwidth and efficiency further for contemporary GPUs and AI accelerators.

Key advantages include high bandwidth per watt, a compact form factor, and reduced memory footprint on the motherboard, contributing to improved overall GPU performance. Compared with conventional GDDR memory, HBM offers substantially higher bandwidth at comparable or lower power, albeit with higher packaging cost and complexity.

Limitations include higher manufacturing and packaging costs, reliance on a silicon interposer, and limited scalability for mainstream consumer devices. Availability tends to be tied to high-end GPUs and specialized accelerators, with supply and yield considerations affecting pricing.

See also: High Bandwidth Memory, GDDR memory, JEDEC standardization.