HBM2

HBM2, or High Bandwidth Memory 2, is a DRAM standard defined by JEDEC as the successor to HBM. It is a 3D-stacked memory technology that uses through-silicon vias to connect multiple DRAM dies into a single high-capacity stack, which is then packaged and connected to a host processor (typically a graphics processor or AI accelerator) via an interposer. The design emphasizes very wide, high-bandwidth access with a compact footprint and relatively favorable power efficiency.

The architecture centers on stacking several DRAM dies into a single memory package. Each stack presents a wide, high-speed interface to the host, and multiple stacks can be deployed to scale bandwidth and capacity. HBM2 increases the data rate per pin compared with its predecessor, enabling higher total bandwidth per stack. The memory dies are connected through TSVs and routed through an interposer, which sits between the memory stacks and the host device to provide short, dense routing paths and a broad memory channel.

HBM2 is used in a range of high-performance computing contexts, including graphics cards, professional GPUs, and AI or HPC accelerators, where very high memory bandwidth per watt is beneficial. Its deployment reduces the physical space required for memory and lowers power consumption relative to traditional GDDR-type memory, at the cost of increased manufacturing and packaging complexity.

Variants and successors such as HBM2E and HBM3 have continued to push data rates and capacities, maintaining the core concepts of 3D-stacked DRAM, TSV interconnects, and interposer-based packaging. See also HBM, JEDEC, and interposer technology.