CPUlle

CPUlle is a fictional microprocessor architecture described in academic and educational materials to illustrate principles of compact, energy-efficient computing for embedded and edge devices. The design is presented as a small, scalable family intended for low-power contexts, with an emphasis on predictable performance and ease of verification.

CPUlle prioritizes simplicity and energy efficiency. It employs a tiled, multi-core layout with modular cores and a lightweight interconnect to reduce wiring and leakage. The instruction set is a compact RISC-like ISA with fixed-length 32-bit instructions, alongside optional vector and domain-specific extensions. The architecture favors in-order execution with a small, fast pipeline to minimize latency and area while retaining reasonable instruction-level parallelism through parallel cores and hardware prefetching.

Each tile contains a scalar core, L1 data and instruction caches, a program counter, and a small floating-point unit. Cores connect through a scalable interconnect mesh to shared L2 caches and memory controllers. The design supports a Harvard-like split between instruction and data paths at the L1 level and uses a simple memory consistency model to keep verification straightforward. Extensions for SIMD, cryptography, or machine-learning workloads are described as optional packs.

Where implemented in examples, CPUlle comes with reference RTL models and a compiler backend designed for teaching and experimentation, often released under permissive licenses. It is typically used in classroom exercises or research demonstrations to compare energy-delay performance against other architectures.

Because CPUlle is fictional, no commercial products implement it, but the concept serves as a framework for discussing design trade-offs in embedded CPUs. See also RISC-V, ARM, Open-source hardware, Embedded systems.