8259

The 8259 refers to Intel’s Programmable Interrupt Controller family, most often the 8259A, used in early x86 and other microprocessor systems to manage hardware interrupts. It became a standard component in many IBM PC compatibles and similar machines, helping the CPU handle multiple interrupt sources efficiently. The 8259 and its descendants provided a scalable approach to interrupt handling before the advent of more advanced APIC systems.

The device presents eight interrupt request inputs (IR0–IR7) and a single interrupt output to the CPU. It can operate in a cascaded master/slave configuration to support up to 15 external IRQs. Internally it maintains registers for pending requests (IRR), in-progress interrupts (ISR), and a mask (IMR) to disable specific lines. Arbitration follows a fixed or rotating priority scheme, allowing higher-priority lines to interrupt lower-priority ones, and it can be configured to respond to edge-triggered or level-triggered signals depending on the system. When an interrupt is acknowledged, the PIC asserts the CPU’s interrupt line and the CPU completes the service routine and signals completion with an End of Interrupt (EOI) command.

Initialization and operation are driven by software through a sequence of commands known as initialization words (ICWs) and operation words (OCWs). ICWs set up the vector base and cascade relationships; OCWs set masking, priority mode, and readback behavior. In typical PC-compatible configurations, the master PIC is mapped at I/O ports 0x20/0x21 and the slave at 0xA0/0xA1, with interrupt vectors commonly starting at 0x08 for the master and 0x70 for the slave.

Legacy and evolution: the 8259 was widely used through the 1990s, but modern systems employ Advanced Programmable Interrupt Controllers (APICs) for scalable, software-managed interrupt routing and more complex topologies. The 8259 concept remains foundational in the study of interrupt architecture.