8259A

The 8259A, or Intel 8259A Programmable Interrupt Controller, is an 8-bit programmable interrupt controller designed for use in early x86 and compatible computer systems. It provides hardware management of interrupt requests (IRQs) and can be configured in a master-slave cascade to handle up to 15 IRQ lines, with eight inputs on each 8259A chip. In typical PC implementations, a master 8259A handles IRQ0–IRQ7 and a slave 8259A is cascaded on IRQ2 of the master to provide IRQ8–IRQ15.

Hardware and interface: The 8259A operates via two 8-bit I/O ports per chip, a command port and a data port. Typical PC I/O addressing places the master at 0x20 (command) and 0x21 (data), with the slave at 0xA0 (command) and 0xA1 (data), though exact addresses may vary by system. The device contains registers for masking, in-service status, and pending requests. It uses an initialization sequence called Initialization Command Words (ICWs) to set the base interrupt vector, establish the cascading relationship, and configure operating modes. Operational control words (OCWs) adjust masking, priority behavior, and EOI handling. End of Interrupt (EOI) commands signal completion of an interrupt service routine; non-specific EOI is issued with a standard command, while specific EOI can target a particular IRQ.

Priority and mode: The 8259A resolves interrupt priorities among its inputs, with options to rotate the priority after each EOI. It can be configured for different triggering modes and 8086/8080-family compatibility via ICW4. The chip provides an Interrupt Request Register (IRR) and an In-Service Register (ISR) to track pending and active interrupts.

Legacy and context: The 8259A was standard in IBM PC compatibles and other early systems. Modern PCs typically replaced it with I/O APICs and local APICs for scalable interrupt handling, but 8259A-compatible devices remain encountered in embedded and retrocomputing contexts.