interrupts

Interrupts are signals that cause a processor to temporarily suspend the execution of the current program in order to attend to an event that requires immediate attention. When an interrupt occurs, the CPU saves its state, and transfers control to a predefined interrupt service routine. After the service routine completes, normal execution resumes. Exceptions, which are synchronous events resulting from the current instruction, are related but distinct from interrupts.

Interrupts can be hardware or software. Hardware interrupts originate from external devices, such as I/O controllers or timers. They may be maskable, meaning they can be enabled or disabled, or non‑maskable (NMI), which cannot be ignored by the processor. Software interrupts are generated by software, for example to request operating system services. Interrupt signaling can be edge-triggered or level-triggered, and dispatch is typically organized by an interrupt controller.

Modern systems employ interrupt controllers, such as PICs or APICs, to prioritize, mask, and route interrupts to the appropriate CPU. An interrupt vector table or similar structure holds the addresses of the corresponding interrupt service routines. In multi‑core systems, the controller distributes interrupts across cores, and techniques like message-signaled interrupts (MSI) improve efficiency.

Handling an interrupt involves acknowledging the signal, saving context, executing the interrupt service routine, and returning control to the interrupted program. ISRs should be short and fast; longer tasks are deferred to later execution, using mechanisms such as bottom halves, tasklets, or schedulers. Interrupts enable responsive I/O and real-time behavior, but add complexity, latency, and potential nondeterminism, which must be managed through careful system design.