Interrupt

An interrupt is a signal to a processor indicating that an event requiring attention has occurred. Interrupts cause the currently executing code to be suspended, the processor’s state to be saved, and control to be transferred to a special routine called an interrupt service routine or interrupt handler. They enable devices and software to signal the CPU asynchronously, improving responsiveness for input/output, timing, and exceptional conditions.

Interrupts come in hardware and software varieties. Hardware interrupts are generated by devices to indicate events such as keystrokes, mouse movement, or timer ticks. They typically use interrupt lines (IRQs) and are managed by an interrupt controller to prioritize and dispatch handling. Software interrupts are generated by code, using an interrupt instruction or through exceptions and traps, and can implement system calls or error handling. Interrupts can be maskable, meaning they can be blocked temporarily, or non-maskable (NMI), which cannot be disabled.

Mechanism: when an interrupt arrives, the processor may complete the current instruction, saves its context, and transfers control to the ISR. The address of the ISR is obtained from an interrupt vector table or a fixed vector. After the ISR finishes, control returns to the interrupted program, typically via a return-from-interrupt instruction. Some systems allow nested interrupts if higher-priority interrupts occur while another is being serviced. Interrupt latency and throughput depend on hardware design, interrupt controller capabilities, and whether masking is employed.

Design considerations include the trade-off between polling and interrupt-driven I/O, the cost of context switching, and interrupt latency. In multiprocessor systems, techniques such as per-CPU interrupt controllers and advanced interrupt mechanisms (e.g., message-signaled interrupts and APICs) help reduce contention. To keep ISRs short, many systems defer heavier work to later processing using deferred handlers or worker queues.