VHDL

VHDL (VHSIC Hardware Description Language) is a high-level language used for describing, modeling, simulating, and synthesizing digital hardware and mixed-signal systems. It enables designers to specify behavior, structure, and timing at multiple levels of abstraction, from abstract algorithms to gate-level implementations.

Originating in the 1980s as part of the U.S. Department of Defense VHSIC program, VHDL was standardized as IEEE 1076 in 1987 and has since undergone several revisions, including ISO/IEC standardization. The most recent major standard is VHDL-2019, with earlier widely used versions such as VHDL-87, VHDL-93, and VHDL-2008.

VHDL supports concurrent execution, explicit timing with wait statements, and a strong-typed design methodology. Core design units include libraries and packages, entities (interfaces) and architectures (implementations), configurations, and packages. Language features include signals and variables, processes, components, generics, records, and user-defined types. The standard library is supplemented by packages such as std_logic_1164 and numeric_std, which provide common data types used in digital design.

VHDL can describe designs at various levels: behavioral, register-transfer level, and structural. Many constructs are synthesizable, allowing descriptive models to be turned into hardware, though some language features are intended primarily for simulation or verification. The design of mixed-language designs and testbenches is common, and designs often integrate with flow tools for simulation, linting, and synthesis.

Common toolchains include dedicated simulators (ModelSim, Questa, GHDL) and synthesis tools from FPGA and ASIC vendors (Xilinx Vivado, Intel Quartus, Cadence, Synopsys). VHDL remains a foundational language in education and industry for documenting and validating digital systems.