synthesizable

Synthesizable refers to hardware description language code or design constructs that can be converted by synthesis tools into a gate-level netlist suitable for implementation in an FPGA or an ASIC. It distinguishes RTL and related code intended to describe actual hardware behavior from code written solely for simulation or verification. Synthesis tools translate synthesizable constructs into logic gates, flip-flops, and routing resources, while honoring constraints such as clocking, timing, and target technology.

Most commonly synthesizable designs are written in languages such as VHDL, Verilog, or SystemVerilog and follow a register-transfer level approach. Typical synthesizable elements include synchronous processes triggered by a clock edge, clear or reset signals, and combinational logic described with continuous assignments or always blocks with explicit sensitivity to inputs. Finite state machines, counters, arithmetic units, and memory blocks can be produced from synthesizable RTL. Real numbers, unbounded loops, and time-based delays are generally not synthesizable and must be avoided or replaced with array indexing, fixed-point representations, or parameterizable constructs.

Common non-synthesizable constructs include delays (#), wait statements, certain timing checks, and many simulation-only system tasks such as $display, file I/O, or $stop. Some language features may be supported only partially or with vendor-specific constraints, so designers often adhere to a conservative subset known to be portable across synthesis tools and target devices.

The workflow typically involves writing synthesizable RTL, verifying behavior with a testbench, and then running a synthesis process to generate a netlist. The resulting design is further optimized for area, speed, and power and mapped to the target FPGA or ASIC technology, followed by place-and-route and timing analysis.