Verilog

Verilog is a hardware description language (HDL) used to model, design, simulate, and verify digital systems. It enables designers to describe hardware at multiple levels of abstraction—from gate-level to register-transfer level (RTL) to high-level behavioral descriptions—and supports both functional simulation and synthesis for implementing circuits in silicon or programmable logic devices. Verilog is widely used for ASIC and FPGA design, as well as for IP cores and verification environments.

Verilog was developed in the 1980s by Gateway Design Automation and became an IEEE standard (IEEE 1364) in the mid-1990s, with subsequent revisions in 1995, 2001, and 2005. SystemVerilog, introduced in the 2000s as an extension to Verilog, adds enhanced verification, interfaces, and object-oriented features; it was standardized separately as IEEE 1800 and has become the dominant language in modern design and verification flows.

Core language features include modules as the basic design unit, with ports for interconnection, nets (wire) and variables (reg, logic) for storage, and procedural blocks such as always and initial for describing behavior. Continuous assignments (assign) model combinational logic, while always blocks model sequential logic. Verilog supports delays and precise timing control, event-driven simulation, and blocking versus nonblocking assignments, which are essential for correct RTL modeling.

Tool support in the industry is extensive, with simulators for verification and synthesis tools for implementation on ASICs or FPGAs. Verilog or SystemVerilog testbenches are used to validate designs before fabrication, and SystemVerilog introduces features such as interfaces, classes, randomization, and the UVM framework for scalable verification. The language remains widely taught and documented, and it forms the basis of many modern digital design workflows.