NoC

Network on Chip (NoC) is a scalable communication subsystem used inside integrated circuits to connect IP cores, memory controllers, and peripherals. It replaces traditional shared buses or point-to-point links with a packet-switched network composed of routers and interconnect links, enabling scalable communication in multi-core and multi-processor System on Chip designs.

A typical NoC consists of routers at network nodes connected by programmable links, plus network interfaces at endpoints. Routers implement input buffers, a crossbar switch, and arbitration and routing logic. Endpoints attach to the network via network interfaces that convert between on-chip protocols and the NoC packet format. Common topologies include 2D meshes, toruses, rings, fat-trees, and butterfly networks. Routing can be deterministic (for example XY routing in a 2D mesh) or adaptive, and many designs employ virtual channels to prevent deadlock.

Benefits include scalable bandwidth, modular design, and improved energy efficiency for many-core communication. NoCs are widely used in multi-core CPUs, GPUs, AI accelerators, and complex embedded SoCs where high inter-core bandwidth and predictable performance are important.

Challenges encompass design complexity, area and power overhead, latency variability, congestion management, quality of service, and integration with cache coherence and memory hierarchy. Verification and fault tolerance are also important, as are heterogeneous integration and secure communication. The NoC concept emerged in the early 2000s as an approach to scalable on-chip communication, providing locality, parallelism, and standardized interfaces for IP cores, memory, and peripherals.