LLSC

LLSC commonly refers to Load-Linked/Store-Conditional, a hardware synchronization primitive used to implement atomic read-modify-write operations in many CPU architectures. The pair enables threads to coordinate access to shared memory without heavy locking by relying on memory reservation concepts.

In typical LLSC operation, a processor first executes a load-linked instruction to read a memory address and establish a reservation on that address. Later, a store-conditional instruction attempts to write back to the same address. The write succeeds only if no other processor has written to that address since the load-linked, in which case the memory is updated atomically. If another write occurred, the store-conditional fails, and the operation may be retried. This mechanism lets software implement atomic increments, test-and-set, fetch-and-add, and compare-and-swap-like operations without traditional locks.

LLSC is supported in several architectures with varying instruction names and nuances. For example, MIPS uses ll and sc, PowerPC uses lwarx/stwcx., and SPARC has similar load-linked/store-conditional pairs. ARM employs a related concept with load-exclusive and store-exclusive instructions, often paired with memory barriers to ensure proper ordering. Modern CPUs may implement LL/SC semantics in hardware in different ways, and compilers or runtimes translate atomic operations into these sequences or fall back to lock-based approaches when necessary.

Limitations of LL/SC include sensitivity to contention and the potential for livelock if many threads repeatedly attempt conflicting updates. They require careful handling of memory ordering and consistency models. When effective, LL/SC can offer scalable atomicity for fine-grained synchronization, though many systems also provide alternative primitives like compare-and-swap or explicit lock mechanisms depending on architecture and context.

Other meanings for LLSC exist in different domains, but the above describes the most common technical use in computer architecture.