LoadLinkedStoreConditional

Load-linked/store-conditional is a family of synchronization primitives used to perform atomic read-modify-write operations without traditional locking. Implemented on several RISC architectures, it typically comprises two instructions: a load-linked (or load-locked) that reads a memory location and establishes a reservation on that address, and a store-conditional that attempts to write a new value only if the reservation remains valid.

The operational idea is that a thread or core first loads a value and marks the address as reserved. Later, it attempts a store-conditional to update the value. The store-conditional will succeed only if no other actor has written to that exact address since the load-linked. If successful, the write occurs and the reservation is cleared; if another write has occurred, the store-conditional fails and no update takes place. In practice, a program detects success or failure and typically retries the sequence by reloading and attempting the update again. Reservations are often cleared by other processors’ writes to the same memory location, by cache coherence events, or by certain memory ordering or interrupt conditions.

LL/SC is commonly used to build lock-free data structures and fine-grained synchronization, such as concurrent stacks, queues, or pointer updates, by allowing an operation to proceed atomically at the hardware level. Compared with compare-and-swap, LL/SC can offer efficient fine-grained updates and can be easier to reason about for certain patterns, but it relies on hardware support and can be sensitive to contention, spurious failures, and memory ordering constraints. If contention is high or the required retry loop is long, performance can degrade. Modern systems often provide similar capabilities via atomic read-modify-write operations or CAS-based primitives, but LL/SC remains a foundational concept in several architectures.