VerilogAMS

Verilog-AMS is a hardware description language designed to model mixed-signal systems, enabling co-simulation of digital and analog components within a single language. It extends the Verilog family with analog and mixed-signal capabilities, drawing on Verilog-A for analog behavioral modeling while preserving Verilog’s digital modeling constructs to describe electronic systems from circuits to subsystems.

Verilog-AMS originated from industry efforts to unify digital and analog modeling and to provide a single, compatible language for mixed-signal design. It was developed by standards bodies and industry groups led by Accellera and later adopted as an IEEE standard. The language is supported by major electronic design automation tools, which implement simulators that can interoperate digital, analog, and mixed-signal models.

The language provides two main modeling styles: analog and digital. Analog modeling covers continuous-time behavior, real-valued signals, differential equations, and analog primitives or controlled sources, while digital modeling handles discrete-event, clocked logic. Modules can contain analog, digital, or mixed blocks, and Verilog-AMS includes interfaces for connecting digital and analog portions of a design. It supports real-number math, time-based constructs, initial conditions, and interfaces to SPICE-like solvers for accurate analog simulation. The result is a framework for designing and validating complex systems such as RF front ends, power electronics, and mixed-signal integrated circuits.

Verilog-AMS remains a reference for mixed-signal modeling, often used when a single language is preferred for both digital control and analog subsystems across a design workflow.