RV64

RV64 is the 64-bit version of the RISC-V Instruction Set Architecture (ISA). It defines a 64-bit general-purpose register file and 64-bit addressing for integer operations, enabling software to use 64-bit virtual addresses and memory pointers. RV64 is part of the open RISC-V standard and, like other variants, is designed to be extended through optional extensions without changing the base ISA. The base integer ISA is RV64I.

Commonly used extensions include M (multiplication and division), A (atomic memory operations), F (single-precision floating point), and D (double-precision). Together, these form a widely implemented 64-bit profile often denoted as RV64IMAFD; many implementations also support the C extension, which provides 16-bit compressed instructions to improve code density, yielding configurations such as RV64IMAFDC. There is also a vector extension (V) for explicit SIMD, available as a separate extension.

Memory addressing in RV64 relies on 64-bit virtual addresses, with several page-table schemes used by different systems. The Sv39 and Sv48 virtual memory schemes are commonly implemented, providing three- or four-level page tables. Physical memory size and alignment are determined by the hardware. RV64 uses 32-bit fixed-length instructions with optional 16-bit compressed instructions when the C extension is enabled.

Adoption and tooling: RV64 is widely supported by Linux and other operating systems on RISC-V, with mature toolchains from GCC and LLVM/Clang, binutils, and simulators such as QEMU. Commercial and open-source cores from vendors such as SiFive, Andes, and others implement RV64 designs. The ecosystem continues to evolve with ongoing work on extensions such as vector, bit-manipulation, and other functionality.