Sv48

Sv48 is a virtual memory addressing mode in the 64-bit RISC-V architecture that provides a 48-bit virtual address space using a four-level page table. It extends the Sv39 scheme to support a larger address space while preserving the same general paging model.

In Sv48, virtual addresses are 48 bits wide and consist of four 9-bit VPN fields (VPN[3:0]) plus a 12-bit page offset. The translation starts at a root page table addressed by the physical page number stored in the SATP register with the mode set to Sv48. A four-level walk traverses from the highest level to the lowest, using VPN[3], VPN[2], VPN[1], and VPN[0]. The upper bits of a virtual address must be the sign-extension of bit 47 to form a canonical address; addresses with non-canonical top bits trap.

Each page-table entry contains flags such as Valid, Readable, Writable, Executable, User, Global, and the A/D (Accessed/Dirty) bits, together with a physical page number (PPN). For a leaf PTE, the PPN specifies the mapped physical page. For non-leaf PTEs, the PPN points to the next-level page table. The four-level walk resolves the final leaf PTE that provides the physical page mapping and the access rights for the translation.

Sv48 commonly uses 4 KiB pages as the base page size, with the possibility of larger pages through multi-level mappings governed by the PTE flags and layout. The scheme emphasizes protection, with per-page permissions and A/D semantics influencing memory behavior and paging activity.

Sv48 is supported by many 64-bit RISC-V implementations and is used in Linux on RISC-V, offering a larger virtual address space compared with Sv39 while maintaining a compatible paged virtual memory model. See also Sv39, Sv57, and Sv64.