MMUs

An MMU, or memory management unit, is a computer hardware component that handles the translation of virtual addresses to physical addresses, and enforces memory protection and access controls. By separating the software-visible address space from the actual physical memory, MMUs enable virtual memory, process isolation, and supervised multitasking.

In modern systems, address translation is typically paging-based. The MMU uses page tables stored in memory, a page table base register, and often a translation lookaside buffer (TLB) to speed repeated translations. A virtual address is divided into fields that index into one or more levels of page tables; the resulting page table entry provides the frame number and access permissions. If a translation cannot be found in the TLB or if the page is not present, the MMU signals a fault (for example, a page fault), and the operating system may bring the page into memory or terminate the access.

The MMU also enforces memory protection by checking permissions for read, write, and execute operations and by applying domain or privilege checks (user vs supervisor modes). It may also provide attributes for each page, such as cacheability and memory-type.

Many CPUs include an integrated MMU. Some architectures support segmentation in addition to paging, although paging is dominant in modern designs. For virtualization, the MMU coordinates with the hypervisor through techniques such as second-level address translation (SLAT) to translate guest addresses to host physical addresses. I/O memory management units (IOMMUs) extend these principles to devices performing DMA and protect system memory from misbehaving devices.