TLB

A Translation Lookaside Buffer (TLB) is a small, fast cache used by a computer’s memory management unit to store recent virtual-to-physical address translations. In systems that use virtual memory, the processor translates virtual addresses to physical frame numbers. The TLB speeds this translation by keeping a subset of these mappings close at hand, reducing the need to access the slower page tables in main memory.

A TLB entry typically contains the virtual page number, the corresponding physical frame number, and access control information such as read, write, and execute permissions. Additional fields may include a valid bit, a global bit, and an address-space identifier (ASID) to distinguish translations belonging to different processes. Many CPUs maintain separate instruction and data TLBs (ITLB and DTLB), while some implement a unified or combined cache. TLBs can be direct-mapped, set-associative, or, in practice, highly associative or even effectively fully associative.

When a memory reference occurs, the processor probes the TLB. If the translation is found (a TLB hit), the physical address is formed quickly and the access proceeds. If not (a TLB miss), the memory management unit must perform a page-table walk to fetch the appropriate page table entry from memory, refilling the TLB with the new translation, and then reissuing the access. Misses can incur substantial latency, especially if the page table spans multiple levels.

TLBs must be maintained coherently whenever page-table entries change. Invalidation or updates may be required on page-table edits or context switches. ASIDs help avoid flushing entire TLBs during context switches, while some architectures use global or per-process entries to optimize performance. Overall, the TLB is a critical component for achieving low-latency virtual memory translation in modern CPUs.