LAPIC

Local APIC, abbreviated LAPIC, is a local interrupt controller built into each CPU core in x86 computer systems. It manages interrupts at the processor level, delivering selected interrupts to its own core and coordinating with the I/O APIC to route external interrupts across multiple processors. The LAPIC is a key component in scalable interrupt handling for symmetric multiprocessing (SMP) systems, supporting features such as Inter-Processor Interrupts (IPIs), timer interrupts, and per-core interrupt prioritization.

The LAPIC is typically memory-mapped into the processor’s address space, commonly at a fixed physical address such as 0xFEE00000. Its register set includes an identification register, a version register, a Task Priority register, an End-of-Interrupt command, and a Local Vector Table that configures local sources of interrupts, including the local timer, the LINT pins, and error signaling. A Spurious Interrupt Vector Register enables the LAPIC to handle spurious interrupts and to enable or disable the LAPIC. The LAPIC can generate IPIs to other CPUs, which is essential for startup sequences of additional processors, synchronization, and scheduling decisions in multi-core systems.

Operation and interaction: During system boot, the operating system configures the LAPICs and the I/O APIC to route device interrupts to the appropriate processor. The Task Priority mechanism masks lower-priority interrupts, while higher-priority interrupts can preempt current handling. After servicing an interrupt, software issues an End-of-Interrupt to clear the in-service status and allow new interrupts.

History and context: The LAPIC is part of Intel’s APIC family, designed to replace older PIC-based interrupt handling. It works in concert with the I/O APIC in modern systems, with variants such as xAPIC and x2APIC supporting larger addressing and enhanced delivery. Operating systems including Linux, Windows, and BSD implement APIC-based interrupt management to support scalable, multi-processor performance.