IPIs

Inter-processor interrupts (IPIs) are a mechanism by which a processor in a multi-core or multi-processor system interrupts another processor to notify it of events or coordinate actions. IPIs enable synchronization, work distribution, and maintenance of cache and memory coherency across cores.

In x86 systems, IPIs are delivered via the Local Advanced Programmable Interrupt Controller (Local APIC) on each core. A sending core writes to the destination core’s Local APIC to trigger a specific interrupt vector. IPIs can be targeted to a single core, to a set of cores, or broadcast to all CPUs. Special-purpose IPIs are used during boot, such as INIT IPI to initialize and Startup IPI to instruct application processors where to start executing. Other IPIs support tasks like scheduling decisions and TLB shootdowns that invalidate translation lookaside buffer entries on other CPUs.

Other architectures implement IPIs using their interrupt controllers; for example, ARM systems use the Generic Interrupt Controller (GIC) to deliver inter-processor interrupts to cores. IPIs are typically short, latency-sensitive interrupts that invoke a handler on the receiving processor and may preempt local work.

Security and performance considerations include the potential for interrupt storms, latency variance, and deadlocks if IPIs interact badly with scheduling or masking. Virtualized environments add vIPI mechanisms to emulate IPIs for guest operating systems, while hypervisors manage delivery to virtual CPUs.

See also: Advanced Programmable Interrupt Controller, Generic Interrupt Controller, symmetric multiprocessing.