xAPIC

xAPIC stands for extended Advanced Programmable Interrupt Controller, the memory-mapped mode of the x86 APIC architecture used to manage interrupts in multiprocessor systems. It relies on two components: the local APIC (LAPIC) embedded in each processor and, in many systems, an I/O APIC that routes external device interrupts to the LAPICs. In xAPIC mode, the LAPIC and I/O APIC registers are accessed through a processor-visible memory map, and processors coordinate by sending inter-processor interrupts (IPIs).

The LAPIC handles local interrupts and IPIs, while the I/O APIC translates device-generated interrupts into LAPIC-delivered interrupts. Interrupt vectors are allocated within a per-processor vector space, and the system can deliver interrupts to one or more CPUs as needed. The design aims to improve scalability over legacy single-processor interrupt controllers by enabling more flexible routing and faster inter-processor communication.

Key characteristics of xAPIC include the use of 8-bit APIC IDs and a 256-entry vector space (0–255) for interrupt delivery. The model supports both fixed and dynamic routing of interrupts, as well as IPIs used for synchronization, task migrations, and startup sequences across CPUs. The architecture also supports a variety of interrupt modes and delivery mechanisms to accommodate different hardware topologies.

x2APIC is a later extension related to xAPIC that expands addressing and uses model-specific registers for APIC state, enabling 32-bit APIC IDs and greater scalability. Modern x86 CPUs and operating systems typically support x2APIC and can operate in either mode depending on hardware and firmware settings. The transition from xAPIC to x2APIC is transparent to most users and software.