IOAPIC

IOAPIC stands for I/O Advanced Programmable Interrupt Controller. It is a component of the x86 APIC architecture designed to manage and route external interrupt signals from hardware devices to the processors in a multiprocessor system. The IOAPIC works alongside Local APICs (one per processor core) to distribute interrupts across CPUs, enabling scalable interrupt handling in multi-core environments.

The core function of the IOAPIC is to provide a redirection table that maps each external interrupt line (IRQ) to a destination LAPIC and interrupt vector. Each redirection entry specifies how the interrupt should be delivered, including the destination LAPIC, the delivery mode, destination mode (physical or logical), mask state, polarity, and trigger mode (edge-triggered or level-triggered). Delivery modes can include fixed, lowest-priority, NMI, or ExtINT, among others. The number of redirection entries varies by device, commonly ranging from 24 to 64 pins depending on implementation.

Access to the IOAPIC is typically through a small memory-mapped I/O (MMIO) window. Software uses an index/select mechanism to choose a register and a data window to read or write that register. Key registers include an identifier, a version register that reports the number of redirection entries, and the redirection entries themselves, which are individually programmable.

In operation, the IOAPIC receives interrupt signals from I/O devices (such as PCI/PCIe devices) and forwards them to the appropriate LAPICs according to the configured redirection entries. It is essential during system initialization and OS runtime configuration to map device IRQs to suitable interrupt vectors on the target CPUs. Some modern devices can deliver interrupts via MSI or MSI-X directly to LAPICs, bypassing the IOAPIC for those paths, but the IOAPIC remains the standard mechanism for legacy external interrupts.