AXI

AXI, standing for Advanced eXtensible Interface, is a high-performance, synchronous, memory-mapped on-chip interconnect standard in ARM’s AMBA family. It is designed to facilitate communication between intellectual property cores within a system-on-a-chip, providing scalable bandwidth, low latency, and support for multiple outstanding transactions.

The AXI protocol uses five independent channels: read address (AR), read data (R), write address (AW), write data (W), and write response (B). Each channel is handshake-based, allowing deep pipelining and simultaneous operations. Transactions can be issued in parallel and may be completed out of order with respect to other transactions, provided that per-ID ordering is preserved. AXI supports burst transfers, including fixed, incrementing, and wrapped bursts, enabling efficient transfer of blocks of data. The width of data, address, and ID signals is configurable, allowing tailoring to specific performance and area requirements.

AXI4 is the widely adopted version for memory-mapped interfaces, offering improved efficiency and support for larger systems. AXI4-Lite is a simplified subset intended for peripheral control registers, with no burst support and fewer channels. AXI3 is an earlier iteration with similar concepts but different signaling. AXI4-Stream is a related, separate protocol used for high-throughput, low-latency streaming data between IP blocks, not for memory-mapped transactions.

In practice, AXI is used to connect CPUs, memories, and peripherals, often via interconnects or switches that facilitate multi-master designs, quality-of-service features, and scalable bandwidth in contemporary SoCs.