AXI4Lite

AXI4-Lite is a subset of the AMBA AXI4 interface designed for simple, memory-mapped register access between a bus master and a slave. It preserves the basic AXI4 read and write channels but removes the complexity of bursting and multiple outstanding transactions, making it suitable for control and status register access in System-on-Chip designs.

Key characteristics of AXI4-Lite include a simplified signaling set, no burst support, and typically a single transaction in flight per slave. Transactions are single-beat both for reads and writes, and there is no explicit transaction ID to track multiple outstanding operations. The protocol provides separate read and write channels, with the master issuing addresses and data while the slave returns responses, and in-order completion is expected.

In operation, a write involves sending a write address and write data, followed by a write response from the slave. A read involves sending a read address and receiving read data along with a read response. The lack of bursts and IDs reduces interconnect complexity and timing constraints, at the cost of lower throughput for large transfers.

Typical use cases include control and status register access in peripherals, GPIO controllers, and other low-bandwidth devices within an SoC. AXI4-Lite is widely supported by vendors and design tools as a convenient interface when high performance is not required. For high-throughput memory transfers or more complex transaction patterns, AXI4-Full (or AXI4) is used instead, offering bursts, multiple outstanding transactions, and richer ordering options.