AXI4

AXI4, or Advanced eXtensible Interface 4, is a memory-mapped interconnect protocol defined as part of ARM's AMBA family. It is designed for high-performance, low-latency communication between components in a system-on-a-chip, supporting scalable bandwidth and high-frequency operation. AXI4 builds on AXI3 with features that favor pipelined, concurrent transfers and out-of-order completion across different transactions.

The interface uses five independent channels: read address (AR), read data (R), write address (AW), write data (W), and write response (B). Each channel employs a valid/ready handshake and carries transaction metadata, including an ID to tag operations. Address channels convey address, burst type, length, and size; data channels carry the actual payload and byte strobes. Responses on the B channel indicate the outcome of write transactions, while the R channel provides read data and responses.

AXI4 supports bursting to improve throughput. Burst types include FIXED, INCR, and WRAP, with burst lengths up to 1–256 beats. The protocol enables multiple outstanding transactions and can deliver responses out of order across different IDs, while preserving per-ID ordering, enabling high utilization of on-chip bandwidth. The separation of address/control and data phases allows deep pipelining and efficient use of memory subsystems.

Variants of AXI4 include AXI4-Lite, a simplified, non-bursting subset for register-style access, and AXI4-Stream, a separate protocol for high-speed streaming without memory-mapped addressing. AXI4 is widely used in modern SoCs and IP cores, supported by numerous vendors and toolchains for on-chip communication.