negedge

Negedge, short for negative edge, is a term used in digital electronics to describe the transition of a signal from a high level (logic 1) to a low level (logic 0) as a clock or control signal falls. The negedge is the falling edge of a clock; the opposite is the posedge, the rising edge.

Many sequential circuits are designed to be edge-triggered, capturing inputs only at a specific clock edge. A negedge-triggered device updates its state on the falling edge of the clock. Common examples include D, JK, or T flip-flops configured to trigger on negedge. Such devices are contrasted with posedge-triggered variants that sample on the rising edge. In practice, designers may choose negedge or posedge behavior to fit timing budgets or to simplify clocking in multi-flop systems.

In hardware description languages, negedge is used to specify a falling-edge sensitivity. For example, an always block in Verilog may be defined as always @(negedge clk) to indicate that the block should run on the clock’s falling edge. Similar constructs exist in VHDL, describing falling-edge triggered processes.

Timing considerations for negedge-triggered elements follow standard synchronous design rules: data must meet the setup time before the triggering edge and be held for the required hold time after the edge. Violations can cause metastability or incorrect sampling. Choosing negedge versus posedge can affect timing margins, skew, and compatibility with other clocked elements.