loadstoremalli

Loadstoremalli is a computer architecture concept in which memory operations are restricted to explicit load and store instructions. All arithmetic and logical operations are performed on data in registers, and processed values are written back to memory only through store instructions. This separation of compute and memory access is characteristic of the model.

In a load-store design, instructions typically operate on a fixed set of registers rather than memory locations. Memory operands are avoided in arithmetic instructions; a memory address is usually formed by adding a base register and an offset, then a load or store instruction transfers data between that address and a register. Immediate operands are often allowed in some instructions to improve efficiency. The design typically relies on a relatively large register file to minimize memory traffic and to enable higher instruction-level parallelism.

The load-store model is a hallmark of many RISC architectures, including MIPS, ARM, RISC-V, and SPARC. It contrasts with traditional memory-to-register architectures where many instructions can reference memory directly. In practice, compilers for load-store systems organize computations as a sequence of register operations, with occasional loads and stores to move data between memory and registers.

Advantages of the model include simpler instruction sets, easier scheduling and pipelining, and more predictable performance. Disadvantages include larger code size due to the extra load/store instructions and potentially increased memory traffic if data locality is poor. The model has influenced modern processor design by prioritizing fast, regular instruction execution and scalable pipeline architectures.