ispLEVER

ispLEVER is a legacy development toolchain from Lattice Semiconductor designed for programming and configuring its ispLSI CPLDs and related devices. The suite provides an end-to-end design flow, including design entry, synthesis, placement and routing, timing analysis, and device programming.

Design entry supports both schematic capture and hardware description languages such as Verilog and VHDL. The included synthesis and place-and-route tools translate the high-level description into a device-specific configuration. The package also includes timing analysis and basic simulation facilities, and is designed to work with common third-party simulators where available.

Target devices include the ispLSI CPLD family and certain other Lattice programmable logic devices from the same era. Programming and in-system programming are performed through a supported programming interface, using configuration files such as JEDEC files (for example, with .jed extensions) or equivalent formats produced by the tool for loading into the device.

ispLEVER has been largely superseded by newer Lattice design environments, notably Diamond. While older projects may still be built with ispLEVER, contemporary development typically uses the newer tools. The ispLEVER line remains referenced in historical documentation and in the maintenance of legacy boards.

In summary, ispLEVER served as an integrated environment for design entry, synthesis, routing, timing, and programming of Lattice’s ispLSI devices, representing an important era in early programmable logic workflows.