depletionload

Depletion load is a design approach used in NMOS logic in which depletion-mode MOSFETs serve as pull-up loads for NMOS switching devices. Depletion-mode transistors are normally on when zero gate bias is applied, providing a current-limited path from the supply to the output node. A typical stage uses a depletion-load transistor in conjunction with an enhancement-mode NMOS transistor as the pull-down switch. The arrangement forms a simple logic gate, commonly an inverter, with other gates realized by network configurations of the same two-device family.

In operation, when the input is low, the pull-down transistor is off and the depletion-load device sources current to the output, producing a high logic level. When the input is high, the pull-down transistor conducts and pulls the output toward ground, producing a low level. The depletion load can be viewed as a built-in, relatively constant current source that helps define the logic levels without a separate resistor. However, because current continues to flow when the output is low, depletion-load NMOS circuits consume static power, unlike some resistor-based arrangements.

Advantages of depletion-load NMOS logic include simpler fabrication and fewer external components for early integrated circuits, as well as decent switching speed and noise margins for its time. Disadvantages center on static power consumption, temperature and process sensitivity, and limited scalability compared with modern CMOS technology. As a result, depletion-load NMOS logic largely fell out of use as power efficiency and integration density improved, though it remains of historical and educational interest and appears in some legacy hardware and literature.