Ycores

Ycores are a family of modular, scalable multicore processors designed for energy-efficient computing in edge, automotive, and data-center workloads. The architecture centers on a Y-shaped network-on-chip topology that connects individual cores to a shared memory subsystem and optional accelerators, enabling scalable bandwidth as cores are added. The concept emphasizes simple, power-aware cores combined with a flexible interconnect to support parallelism and heterogeneity.

Each Ycore contains a compact, RISC-like ISA optimized for low power, a small multithreaded pipeline, and a private L1 instruction and data cache. Cores can run independently or in coordinated groups, with a hardware scheduler that can switch among threads to hide latency. The design favors software portability through common toolchains.

The Y-shaped interconnect forms a three-branch topology in which cores connect to parent and child nodes through a configurable fabric. The arrangement aims to scale bandwidth and reduce contention, using a directory-based coherence protocol to keep caches coherent across all cores. The topology supports modular expansion by adding more cores without redesigning the network.

Memory hierarchy typically includes private L1 caches, a scalable shared L2 or L3 cache, and coherence-enabled memory controllers. Ycores may integrate optional accelerators such as AI blocks, DSP units, or cryptography logic, enabling domain-specific performance without abandoning a single programming model.

Software support centers on standard toolchains, with LLVM-based compilers and operating systems that provide thread scheduling and accelerator drivers. Although Ycore designs have shown favorable energy efficiency on multi-threaded workloads, adoption remains primarily within research and specialized embedded markets, with ongoing work to optimize area, power, and ecosystem maturity.