Ycores
Ycores are a family of modular, scalable multicore processors designed for energy-efficient computing in edge, automotive, and data-center workloads. The architecture centers on a Y-shaped network-on-chip topology that connects individual cores to a shared memory subsystem and optional accelerators, enabling scalable bandwidth as cores are added. The concept emphasizes simple, power-aware cores combined with a flexible interconnect to support parallelism and heterogeneity.
Each Ycore contains a compact, RISC-like ISA optimized for low power, a small multithreaded pipeline, and a
The Y-shaped interconnect forms a three-branch topology in which cores connect to parent and child nodes through
Memory hierarchy typically includes private L1 caches, a scalable shared L2 or L3 cache, and coherence-enabled
Software support centers on standard toolchains, with LLVM-based compilers and operating systems that provide thread scheduling