VHDLAMS

VHDL-AMS (VHDL for Analog and Mixed-Signal) is an extension of the VHDL hardware description language that enables integrated modeling of continuous-time analog circuits and discrete-event digital systems within a single language. It is used to design and simulate mixed-signal hardware such as mixed-signal integrated circuits, sensors, and feedback control blocks.

The language maintains the core VHDL syntax while adding features for analog behavior. It introduces physical quantity types, units, and real-valued signals, along with constructs to describe electrical networks and continuous-time dynamics. Interfaces between analog and digital parts are provided through specialized port declarations and signal domains.

Key concepts include analog processes that describe time-dependent relationships, differential equations, and electrical laws, and digital processes that handle clocked behavior. VHDL-AMS supports hierarchical design, re-usable components, and mixed-domain connectivity, allowing designers to model an op-amp, a filter, or a microcontroller with analog peripherals in one model.

Simulation in VHDL-AMS typically uses solvers for continuous-time dynamics in concert with discrete-event simulators. It supports co-simulation with SPICE-based device models, enabling transistor- or circuit-level fidelity within system-level verification and timing analysis.

VHDL-AMS is standardized as an extension of the VHDL language and is supported by several commercial EDA tools. It is used in academia and industry for research and development of analog/mixed-signal circuits, and for teaching mixed-domain modeling concepts.

See also: VHDL, SPICE, mixed-signal design, electrical network modeling.