TLBmisses

TLBmisses refer to events when a memory reference cannot be translated by the processor’s Translation Lookaside Buffer (TLB). The TLB is a small, fast cache of virtual-to-physical address mappings used by the memory management unit to speed up address translation. When a memory access occurs, the MMU first checks the TLB for the translation. If the entry is found, the access proceeds quickly (TLB hit). If not, a TLB miss occurs.

On a TLB miss, the hardware or operating system must perform a page table walk to obtain the appropriate translation from the system’s page tables. If the page table entry for the requested virtual address is valid and the page resides in physical memory, the translation is loaded into the TLB and the memory access is retried. If the page is not present in physical memory, a page fault occurs, triggering the OS to bring the page from secondary storage, update page tables, and restart the access after the fault is serviced.

TLB misses are often described using a minor/major distinction. A minor miss occurs when the page is not in the TLB but is in memory, requiring a page table walk to obtain the translation. A major miss typically refers to a page fault, where the required page must be loaded from disk or another backing store before the translation can be completed.

Performance and architecture considerations surround TLB misses. Misses add latency relative to TLB hits and can become a bottleneck if the TLB is small or the working set requires many translations. Mitigations include larger or more associative TLBs, larger page sizes (huge pages), TLB prefetching, hardware page-walk support, and optimizations in operating systems and architectures. In virtualized environments, additional layers of translation (such as EPT/NPT) and TLB invalidation can influence miss behavior and overhead.