FIQ

FIQ, or Fast Interrupt reQuest, is a high-priority interrupt mechanism in ARM architecture designed to provide fast, deterministic response to time-critical hardware events. It sits alongside IRQ (Interrupt Request) as one of the primary exception types invoked by hardware or software triggers. Compared to IRQ, FIQ typically has higher priority and a shorter handling latency.

When an FIQ is asserted, the processor switches to FIQ mode, which uses a dedicated banked register set to minimize context saving. In many ARM implementations, registers R8 through R12, along with the stack pointer (R13) and link register (R14), are banked for FIQ mode. The processor also enters a fast interrupt vector at a fixed address (commonly 0x1C in the ARM exception vector table), where the FIQ handler resides. The current program status register (CPSR) controls masking of interrupts with I (IRQ disable) and F (FIQ disable) bits; enabling FIQ requires leaving FIQ unmasked and not disabling it.

FIQ handlers are typically designed to execute quickly, performing minimal work and deferring longer tasks to other software. Because of the banked registers and rapid entry, FIQ is well suited to time-sensitive peripherals such as high-speed peripherals or real-time data streams. However, many modern ARM cores have evolved interrupt controllers and may not expose FIQ as a distinct path, instead providing high-priority interrupts via configurable controllers; in such cases, the traditional FIQ path may be used only in legacy systems.

See also: ARM architecture, interrupt handling, IRQ, vector table.