BUFGCTRL

BUFGCTRL is a global clock buffer primitive used in Xilinx field‑programmable gate arrays (FPGAs). It extends the functionality of the basic BUFG buffer by providing programmable control over multiple clock sources, a clock enable, and a clock select input. This allows designers to switch between different clock signals on the global distribution network while maintaining the phase relationship and minimizing skew.

The BUFGCTRL primitive is typically instantiated in a design as a clocking device that feeds a clock net to other logic elements. It has two clock inputs, C0 and C1, a SELECT input that chooses which of the two sources is routed to the output, a CE (clock enable) input that can mask the selected clock, and a CLOCKSUSPEND input that temporarily suspends the clock output. The output is routed to the global clock network (BUFG) and may be inverted by the optional INVERTED attribute. The device also includes a LOCKED output that indicates when the selected clock is stable and its phase is achieved.

Because BUFGCTRL is part of the global clock distribution fabric, it offers very low skew and consistent timing characteristics, making it ideal for clock domain crossing, clock gating, or clock source selection in high‑performance digital systems. It is commonly employed in designs that require dynamic clock management, such as PLL or MMCM‑based clocking, or applications that need to switch between multiple data rates or operating modes. The primitive is supported by Xilinx’s Vivado Design Suite and can be configured through constraints files or Vivado’s clocking wizard tools.

Overall, BUFGCTRL provides designers with a flexible, high‑speed, low‑skew pathway for multiple clock signals, enabling dynamic control and efficient clock distribution in modern FPGA applications.