AXIStream

AXIStream is an interface standard defined by the Advanced eXtensible Interface (AXI) family for high‐throughput, unidirectional streaming data transfer. Unlike the memory‑mapped AXI4 and AXI4-Lite protocols, AXIStream does not use an address bus; instead it provides a simple, point‑to‑point link between a master source and a slave sink. The core signals are TDATA, TVALID, TREADY, and optional TLAST, TKEEP, TSTRB, TID, TDEST, and TUSER. The handshaking works with TVALID asserted by the master when data is available and TREADY asserted by the slave when it is ready to accept data; data is transferred on the rising edge of the clock when both signals are high. The TLAST signal is used to indicate the end of a packet or frame, allowing packet‑delimited traffic such as Ethernet or MPEG streams to be demarcated on the bus.

Because AXIStream removes address and control overhead, it achieves very low latency and high clock rates, making it suitable for applications that demand continuous, bulk data movement. Typical use cases include video and image processing pipelines, audio and sensor data streaming, networking and packet processing, and in‑chip DMA engines. Vendors such as Xilinx and Intel (Altera) provide AXI‑Stream core IP blocks and support within their FPGA development tools, enabling designers to integrate stream interfaces into custom logic or high‑level programming environments with minimal glue logic. The simplicity of the protocol also facilitates reliable interconnects in multi‑oriented system‑on‑chip (SoC) designs, where a dedicated streaming path can coexist with memory‑mapped control interfaces.