ADPLL
An all-digital phase-locked loop (ADPLL) is a digitally implemented version of the conventional phase-locked loop in which the major blocks are realized with digital circuitry. In an ADPLL, the reference clock is compared with a locally generated clock by a digital phase detector or phase-frequency detector, and the resulting digital error signal is processed by a digital loop filter to produce a control word for the digitally controlled oscillator. The local oscillator is typically realized as a numerically controlled oscillator or a digitally programmable delay line, producing a clock with tunable frequency and phase. Frequency synthesis is often achieved through a feedback divider in the digital domain, with fractional-N functionality implemented via digital sigma-delta modulation.
Architecture and operation: A typical ADPLL chain includes a digital phase detector, a digital loop filter,
Advantages and challenges: ADPLLs offer strong process, voltage, and temperature portability and easy integration in CMOS
Applications: ADPLLs are used in high-density integrated circuits requiring flexible, stable clock generation, such as high-speed