clockdomain

A clock domain is the portion of a digital circuit whose storage elements are clocked by a single clock signal. In many chips, several clock domains coexist, each driven by its own clock or by different clock frequencies or phase relationships. Signals crossing from one domain to another must be treated with care to avoid timing hazards.

The main problem in clock-domain crossings is metastability. If a flip-flop in the destination domain captures an asynchronously changing signal, its output may resolve to a metastable state for an uncertain time, potentially propagating glitches to downstream logic. The risk is higher when domains run at different frequencies, have skew, or transfer multi-bit data. Metastability probability decreases with additional synchronization stages in the receiving domain.

Common mitigation techniques include using a synchronizer, typically two flip-flops in the destination clock domain to stabilize a single-bit signal before use; employing handshake schemes that coordinate data transfer with request and acknowledge signals; and moving data through asynchronous or dual-clock FIFOs that use carefully synchronized pointers, often Gray-coded, to prevent hazards. For simple control signals, direct toggling or level-sensitive handshake can suffice if well managed.

Design practice also involves managing clock skew, duty cycle, resets, and power-down conditions so that crossing signals do not create glitches or indeterminate states. Verification is essential and usually includes clock-domain crossing analysis, simulation of cross-domain interactions, and formal checks to identify potential metastability paths or unsafe data transfers.

Overall, clock-domain design seeks reliable inter-domain communication while maintaining performance. Clear boundary definitions, appropriate synchronization, and robust verification are standard parts of contemporary digital design processes.